Method of programming a non-volatile memory cell using a substrate bias
US6438031B1 · kind B1 · utility
83Cited by
4References
35Claims
0Family size
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Inventor
Key dates
| Filing date | Oct 26, 2000 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Oct 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0475
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell that includes a substrate that has a first region and a second region with a channel therebetween. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge, wherein the first region is doped to such an extent that electric fields are reduced at the locations in the substrate where impact ionization occurs during programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.