Dual buffer chamber cluster tool for semiconductor wafer processing
US6440261B1 · kind B1 · utility
413Cited by
66References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 1999 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | May 25, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Apparatus for multi-chambered semiconductor wafer processing comprising a polygonal structure having at least two semiconductor process chambers disposed on one side. An area between the process chambers provides a maintenance access to the semiconductor processing equipment. Additionally, the apparatus may be clustered or daisy-chained together to enable a wafer to access additional processing chambers without leaving the controlled environment of the semiconductor wafer processing equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.