DRAM technology of storage node formation and no conduction/isolation process of bottle-shaped deep trench
US6440792B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 19, 2000 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Apr 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0387
Abstract
An improved method for reducing the cost of fabricating bottle-shaped deep trench capacitors. It includes the steps of: (a) forming a deep trench into a semiconductive substrate; (b) filling the deep trench with a first dielectric material to a first predetermined depth; (c) forming a silicon nitride sidewall spacer in the deep trench above the dielectric layer; (d) removing the first dielectric layer, leaving the portion of the substrate below the sidewall spacer to be exposed; (e) using the sidewall spacer as a mask, causing the exposed portion of the substrate to be oxidized, then removing the oxidized substrate; (f) forming an arsenic-ion-doped conformal layer around the side walls of the deep trench, including the sidewall spacer; (g) heating the substrate to cause the arsenic ions to diffuse into the substrate in the deep trench not covered by the sidewall spacer; (h) removing the entire arsenic-ion-doped layer; (i) forming a conformal second dielectric layer covering the surface of the deep trench including the sidewall spacer, then filling the deep trench with a first conductive material to a second predetermined depth which is above the first predetermined depth; (j)removi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.