Method for etching passivation layer of wafer
US6440859B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1998 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | May 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/304
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an improved method for etching a groove n the uppermost layer of a semiconductor wafer, a conventional anisotropic etch is performed to achieve a narrow groove and an isotropic etch is performed to widen the groove at the device surface and thereby round the edges where the walls of the groove meet the surface of the wafer. During a later step of applying a protective tape to the device side of the wafer to protect it during a step of grinding the back of the wafer, the rounded edges of the groove are unlikely to cut through the adhesive layer of the tape and thereby cause particles of adhesive to remain on the wafer surface when the tape is removes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.