SOI device and method of fabrication
US6441436B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2000 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Nov 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.