Scribe line structure for preventing from damages thereof induced during fabrication
US6441465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1999 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Feb 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A scribe line structure of a semiconductor wafer is provided in the invention. The semiconductor wafer has a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines to separate a plurality of chips from each other. According to the invention, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure comprises a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure. The cavities of the scribe line structure are capable of relieving internal stress of the scribe lines and arresting possible cracks induced during scribe line manufacture. Thereby, peeling, delamination and dielectric fracture of the scribe lines induced during the wafer manufacture can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.