Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data
US6442653B1 · kind B1 · utility
15Cited by
6References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 24, 1999 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Jun 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processing unit, a distributed memory including a local memory and a remote memory having differing access latencies, and a cache coupled to the processing unit and to the distributed memory. The cache includes data storage and a plurality of latency indicators that each indicate an access latency to the distributed memory for associated data stored in the data storage. As a result, transactions related to cached data can be efficiently routed and addressed and efficient victim selection and deallocation policies can be implemented in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.