Techniques for improving memory access in a virtual memory system
US6442666B1 · kind B1 · utility
42Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 26, 2000 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Jan 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to the present invention, methods and apparatus for reducing memory access latency are disclosed. When a new entry is made to translation look aside buffer, the new TLB entry points to a corresponding TLB page of memory. Concurrently with the updating of the TLB, the TLB page is moved temporally closer to a processor by storing the TLB page in a TLB page cache. The TLB page cache is temporally closer to the processor than is a main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.