Method and product for improved use of low k dielectric material among integrated circuit interconnect structures
US6444564B1 · kind B1 · utility
5Cited by
33References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 23, 1998 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Nov 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76837
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for forming a liner upon spaced interconnect structures arranged upon a semiconductor topography. An oxide layer may be deposited to form the liner. The spaced interconnect structures may each include an interlevel dielectric portion arranged upon a metal interconnect portion, with gaps defined between adjacent interconnect structures. A low k dielectric material may be deposited over the interconnect structures such that the low k material substantially fills the gaps between adjacent interconnect structures. The low k dielectric material may then be planarized, preferably by chemical mechanical polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.