Process for alloying damascene-type Cu interconnect lines
US6444567B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jan 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76849
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The reliability and elecrtromigration resistance of planarized metallization patterns, e.g., of copper, in-laid in the surface of a layer of dielectric material, are enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one thin layer comprising at least one alloying element for the metal of the features, and then uniformly diffusing at least a minimum amount of the at least one thin layer for a minimum depth below the upper surfaces of the metallization features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer. The invention finds particular utility in “back-end” metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.