Interfacial oxidation process for high-k gate dielectric process integration
US6444592B1 · kind B1 · utility
137Cited by
9References
22Claims
0Family size
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Key dates
| Filing date | Jun 20, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jul 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 å; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.