Dynamic data amplifier with built-in voltage level shifting
US6445621B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Apr 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read data latch circuit that provides a level shift between internal and external voltages that does not require added circuitry dedicated to equalizing or level shifting the data latch nodes. Data lines are provided having a higher capacitance than the capacitance of the data latch nodes. The data latch nodes are connected to the data lines through a switch. When the switch is open, an equalization charge is shared between the data lines and the latch nodes. The voltage for providing the equalization charge and data signals internal to the chip is lower than the data output signals provided to external circuitry by the data latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.