Memory device redundancy selection having test inputs
US6445625B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Sep 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices having redundancy selection circuitry are adapted to introduce test input signals into the redundancy selection path. The memory devices include a redundancy selection circuit having a latch for latching an incoming redundancy match signal. The latch includes a pair of reverse-coupled inverters. The latch is further coupled to receive one or more test input signals. The latch is responsive to one or more control signals to selectively generate the latched match signal from the incoming redundancy match signal or one of the test input signals. When the latched match signal is generated from the incoming redundancy match signal, the logic level of the latched match signal is independent of the logic level of any of the test input signals. When the latched match signal is generated from one of the test input signals, the logic level of the latched match signal is independent of the logic level of the incoming redundancy match signal. Such latch circuits are useful for controlling selection of a redundant element in a memory device during testing without significantly impacting the speed path of the redundancy selection circuitry during normal operation of the memory dev…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.