Patent · US Expired

Method for carrying out a burn-in process for electrically stressing a semiconductor memory

US6445630B2 · kind B2 · utility

13Cited by

12References

7Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Kamel Ayadi · Puchheim, DE
Jürgen Lindolf · Friedberg, DE
Nedim Oezoguz-Geissler · Taufkirchen, DE

Key dates

Filing date	Mar 23, 2001
Grant date	Sep 3, 2002
Priority date	—
Expiry date	Mar 23, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/50
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit configuration is described that has a first voltage terminal, a second voltage terminal and a control input. A reference-ground potential is applied to the first voltage terminal and an operating voltage is applied to the second voltage terminal. The control input is supplied with a control voltage, the control voltage assumes voltage values which alternate between the reference-ground potential and the operating voltage. The alternation of the control voltage has the effect that components such as transistors and inverter that are present in the circuit configuration are active and thereby experience an accelerated aging process in order to stabilize the threshold voltage of the MOS transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.