Cache prefetching of L2 and L3
US6446167B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. The prefetch request may include a signal notifying the third level cache to also prefetch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.