Applying epitaxial silicon in disposable spacer flow
US6448129B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2000 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jan 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.