Memory interface having source-synchronous command/address signaling
US6449213B1 · kind B1 · utility
70Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2000 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Sep 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface scheme reduces propagation delay by utilizing source-synchronous signaling to transmit address/command information to memory devices. A memory module in accordance with the present invention may include an address/command buffer that samples address/command information responsive to an address/command strobe signal and then passes the address/command information to a memory device on the module. A retiming circuit may be used to control the timing of read-return data from a memory device on the module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.