Multiple loadlock system
US6450750B1 · kind B1 · utility
41Cited by
48References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/908
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe system. In one embodiment, the holding chamber has a transfer robot which holds a stack of wafers for subsequent transfer to the processing chambers of the mainframe processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.