Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual
US6451647B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2002 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Mar 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a process of fabricating a semiconductor device, including steps of providing a first semiconductor wafer; depositing on the first semiconductor wafer a layer comprising a high-K dielectric material layer; depositing on the layer comprising a high-K dielectric material a polysilicon or polysilicon-germanium layer; and forming a gate stack by plasma etching both a portion of the polysilicon or polysilicon-germanium layer and a portion of the layer comprising a high-K dielectric material in a single chamber. In one embodiment, the step of plasma etching is carried out without moving the first wafer from the chamber. In another embodiment an unwanted residual high-K dielectric material is removed by applying a low power plasma treatment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.