Scheme for delay locked loop reset protection
US6452431B1 · kind B1 · utility
20Cited by
4References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Nov 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for operating a delay locked loop during a reset. The systems and methods provide for activating a reset mode signal to prevent a phase lock signal from forcing the DLL out of a reset, and deactivating the reset mode signal only after at least one shifting operation is performed to allow the phase lock signal to correctly allow the DLL to be out of the reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.