Reduced signal test for dynamic random access memory
US6453433B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1999 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Mar 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method and apparatus for testing a semiconductor memory having a plurality of memory cells arranged in rows and columns and a plurality of sense amplifiers, each for amplifying memory cell signals of a common row or column. In an illustrative embodiment of the method, a voltage level or test pattern is written into at least one target cell of the memory cells. A word line coupled to the target cell is then activated and subsequently deactivated, to thereby modify the voltage level stored in the cell, while the associated sense amplifier is prevented from refreshing the cell as the word line is activated, e.g., by disabling the sense amplifier. A test bit line voltage is then applied to a bit line coupled to the cell to charge the same. Data is then read from the target cell with settings of the associated sense amplifier enabled, and compared to the original voltage level written into the cell. The process is repeated for different test bit line voltages. The method can be used to determine the signals at the sense amplifiers during normal operation of the memory, without employing complex and costly picoprobes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.