Method of making high density semiconductor memory
US6455367B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2000 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Dec 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) includes a plurality of memory cells aligned with one another along a pair of wordlines with each wordline being connected to access alternate ones of the memory cells. The DRAM has aligned memory cells having cell areas of 6F2 yet exhibiting substantially the same superior signal-to-noise performance found in DRAM's having staggered 8F2 memory cells. The DRAM memory cells are formed by transistor stacks which are aligned along and interconnected by wordlines extending between and included within the transistor stacks. By forming the wordlines as a part of the transistor stacks, the wordlines are narrow ribbons of conductive material. During formation of the transistor stacks, the wordlines are connected so that a first wordline controls access transistors of every other one of the memory cells and a second wordline controls the access transistors of the remaining memory cells. Thus, the first wordline accesses a first series of alternate memory cells, such as the odd memory cells, and the second wordline accesses a second series of alternate memory cells, such as the even memory cells, with the first and second series of memory cells being int…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.