Nucleation for improved flash erase characteristics
US6455372B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 14, 2000 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Sep 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/661
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for improving the erase speed and the uniformity of erase characteristics in erasable programmable read-only memories. This result is achieved by forming polycrystalline floating gate layers with optimized grain size on a tunnel dielectric layer. Nucleation sites are formed by exposing the tunnel dielectric layer to a first set of conditions including a first temperature and a first atmosphere selected to optimize nucleation site size and distribution density across the tunnel dielectric layer. A polycrystalline floating gate layer is formed on top of the nucleation sites by exposing the nucleation sites to a second set of conditions including a second temperature and a second atmosphere selected to optimize polycrystalline grain size and distribution density across the polycrystalline floating gate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.