Fabricating plug and near-zero overlap interconnect line
US6455921B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrically conductive plug on a semiconductor workpiece. A dielectric layer is deposited on the workpiece, and a cavity is etched in the dielectric. An etchant-resistant material is deposited on the wall of the cavity adjacent the cavity mouth so as to form an inwardly-extending lateral protrusion, the etchant-resistant material being resistant to etching by at least one etchant substance which etches said electrically conductive material substantially faster than it etches the etchant resistant material. The cavity is filled by an electrically conductive material. In another aspect of the method, the etchant-resistant material can be omitted. Instead, upper and lower portions of the cavity are etched anisotropically and isotropically, respectively, so as to form a lower portion of the cavity that is wider than the upper portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.