Method and structure for in-line monitoring of negative bias temperature instability in field effect transistors
US6456104B1 · kind B1 · utility
26Cited by
7References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 18, 1999 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Aug 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2621
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A MOSFET test structure and associated electronics for rapidly heating the MOSFET gate oxide and for applying a stress voltage to the gate. The structure has at least one polysilicon gate with two spaced contacts that permit a heating current to flow through the gate thus rapidly raising the gate temperature to a desired level. External electronics permit applying a measured stress voltage to the gate. The structure is particularly useful in NBTI testing of p-MOSFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.