Method and program product for modeling circuits with latch based design
US6457161B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | May 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of and computer program product for modeling a logic circuit having combinational logic and latches, in which the latches are clocked by one of a first clock phase, a second clock phase or a pulse derived from the second clock phase, a subset of latches being scannable, comprises, for each latch in the logic circuit, associating the latch with one of the first and second clock phase; and when latch is associated with the first clock phase, modeling the latch as a buffer connected between the data input and output of latch; and when the latch is associated with the second clock phase, modeling the latch as an edge-triggered flip-flop having the same data input, data output and clock input as the latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.