Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
US6458662B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 4, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Apr 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A method of fabricating a semiconductor device, having an asymmetrical dual-gate MOSFET with a silicon-germanium (SiGe) channel, involving: patterning a silicon-on-insulator (SOI) wafer with a photoreist layer, wherein the SOI structure comprises a silicon dioxide (SiO2) layer, a silicon (Si) layer deposited on the SiO2 layer, and a silicon nitride (Si3N4) layer deposited on the Si layer; initiating formation of a SiGe/Si/SiGe sandwich fin structure from the SOI structure; completing formation of the SiGe/Si/SiGe sandwich fin structure; depositing a thick gate material layer on the SiGe/Si/SiGe sandwich fin structure; forming an asymmetrical dual-gate; and completing fabrication of the semiconductor device, and a device thereby formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.