Method of programming a non-volatile memory cell using a drain bias
US6459618B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Jun 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate and applying a second constant voltage across the first region so as to generate a first charge injection region. The application of the second constant voltage is discontinued while simultaneously applying a third constant voltage across the first region so that a second charge injection region is generated that is larger than the first charge injection region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.