Janet Wang
23Patents
17h-index
24Co-inventors
73Inventor score
Filing activity: Dec 18, 1997 → Aug 19, 2002
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6269023A | Method of programming a non-volatile memory cell using a current limiter | Physics | 139 | Expired |
| US6266281A | Method of erasing non-volatile memory cells | Physics | 132 | Expired |
| US6541816B2 | Planar structure for non-volatile memory devices | Emerging Cross-Sectional Technologies | 83 | Expired |
| US6567303B1 | Charge injection | Physics | 76 | Expired |
| US6618290B1 | Method of programming a non-volatile memory cell using a baking process | Physics | 70 | Expired |
| US6590811B1 | Higher program VT and faster programming rates based on improved erase methods | Physics | 68 | Expired |
| US6468865B1 | Method of simultaneous formation of bitline isolation and periphery oxide | Electricity | 53 | Expired |
| US6456533B1 | Higher program VT and faster programming rates based on improved erase methods | Physics | 50 | Expired |
| US6555436B2 | Simultaneous formation of charge storage and bitline to wordline isolation | Emerging Cross-Sectional Technologies | 44 | Expired |
| US6456536B1 | Method of programming a non-volatile memory cell using a substrate bias | Physics | 43 | Expired |
| US6459618B1 | Method of programming a non-volatile memory cell using a drain bias | Electricity | 41 | Expired |
| US6456531B1 | Method of drain avalanche programming of a non-volatile memory cell | Physics | 40 | Expired |
| US6172909A | Ramped gate technique for soft programming to tighten the Vt distribution | Physics | 38 | Expired |
| US6490205B1 | Method of erasing a non-volatile memory cell using a substrate bias | Physics | 32 | Expired |
| US5888867A | Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration | Electricity | 30 | Expired |
| US6465306B1 | Simultaneous formation of charge storage and bitline to wordline isolation | Emerging Cross-Sectional Technologies | 30 | Expired |
| US6331953A | Intelligent ramped gate and ramped drain erasure for non-volatile memory cells | Electricity | 18 | Expired |
| US6233175A | Self-limiting multi-level programming states | Physics | 17 | Expired |
| US6465303B1 | Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory | Electricity | 13 | Expired |
| US6331952A | Positive gate erasure for non-volatile memory cells | Physics | 11 | Expired |
| US6025240A | Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices | Electricity | 9 | Expired |
| US6188101A | Flash EPROM cell with reduced short channel effect and method for providing same | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6410956B1 | Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.