Configuration for implementing redundancy for a memory chip
US6459631B2 · kind B2 · utility
1Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Jul 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a configuration for implementing redundancy for a memory chip, in which a fuse bank is connected to a comparator via a redundancy predecoder so that predecoded addresses can be compared with one another in the comparator and undecoded addresses can be stored in the fuse bank. This provides for a low-power and space-saving design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.