Apparatus and method for increasing test flexibility of a memory device
US6459635B1 · kind B1 · utility
16Cited by
6References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Oct 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation control circuitry for altering a sequence of internal memory operations in a memory device while in a test mode. The operation control circuitry includes a code circuit for providing an operation code in accordance to a user programmable code. An operation control circuit generates operation control signals in response to receiving command signals from a command circuit included in the operation control circuitry. The operation control signals generated by the operation control circuit control the occurrence of the internal memory operations according to an operation code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.