System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism

US6460115B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• James Allan Kahle · Austin, US
• Michael John Mayfield · Austin, US
• Francis Patrick O'Connell · Austin, US
• David Scott Ray · Georgetown, US
• Edward John Silha · Austin, US
• Joel M. Tendler · Austin, US

Key dates

• Filing date: Nov 8, 1999
• Grant date: Oct 1, 2002
• Expiry date: Nov 8, 2019

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/6028
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.