Multichip module having a stacked chip arrangement
US6461897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | May 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01087
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.