SOI wafers and methods for producing SOI wafer
US6461939B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2000 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Nov 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to the present invention, there are provided an SO wafer wherein surface roughness of an SOI layer surface of the SOI wafer is 0.12 nm or less in terms of RMS value and/or interface roughness of an interface between the SOT layer and a buried oxide layer of the SOI wafer is 0.12 nm or less in terms of RMS value, and a method for producing an SOI wafer, which comprises mirror-polishing an SOI wafer, removing a native oxide film on a surface of the wafer or forming a thermal oxide film having a thickness of 300 nm or more on the surface and removing the thermal oxide film, and subjecting the wafer to a heat treatment in an atmosphere of 100% hydrogen or a mixed gas atmosphere of argon and/or nitrogen containing 10% or more of hydrogen by using a rapid heating and rapid cooling apparatus. Thus, there can be obtained an SOI wafer of high quality having surface roughness of the SOI layer surface and interface roughness of the SOI/BOX interface that affect extremely little on the fluctuation of device characteristics of MOS devices fabricated by using the SOI wafer, such as dielectric breakdown voltage, threshold voltage and carrier mobility, and a method for producing the same…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.