Yield improvement of dual damascene fabrication through oxide filling
US6461955B1 · kind B1 · utility
28Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2000 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Mar 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76805
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual damascene process. After the via etch, a via protect layer (114) is deposited in the via (112). The via protect layer (114) comprises a material that has a dry etch rate at least equal to that of the IMD (108) and a wet etch rate that is approximately 100 times that of the IMD (108) or greater. Exemplary materials include PSG, BPSG, and HSQ. The trench pattern (120) is formed and both the via protect layer (114) and IMD (108) are etched. The remaining portions of the via protect layer (114) are then removed prior to forming the metal layer (122).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.