Material removal method for forming a structure

US6461967B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Zhiqiang Wu · Plano, US
• Li Li · Meridian, US
• Thomas A. Figura · Boise, US
• Kunal R. Parekh · Boise, US
• Pai-Hung Pan · Boise, US
• Alan R. Reinberg · Boise, US
• Kin F. Ma · Boise, US

Key dates

• Filing date: Jul 16, 2001
• Grant date: Oct 8, 2002
• Expiry date: Jul 16, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0223
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.