Multi-film capping layer for a salicide process
US6462390B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2000 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Sep 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-film capping layer having a cobalt layer, a barrier layer, and a stuffing layer is disclosed, wherein the barrier layer isolates the cobalt layer from the stuffing layer. The multi-film capping layer is formed on a gate transistor and applicable to a self-aligned silicide (salicide) process, so that a sheet resistance of the salicide layer on conductive regions of the gate transistor is significantly reduced. The stuffing layer further prevents entry of oxygen or moisture to the salicide layer, thus no cobalt oxide is formed when RTP is performed. Without formation of the cobalt oxide, the salicide process is free from the bridging issue and the filament issue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.