Configurable memory structures in a programmable logic device
US6462577B1 · kind B1 · utility
61Cited by
21References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2001 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Jan 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.