Semiconductor container structure with diffusion barrier
US6465828B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/711
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Container structures for use in integrated circuits and methods of their manufacture. The container structures include a bottom conductive layer, a top conductive layer and a dielectric layer interposed between the bottom conductive layer and the top conductive layer. The container structures further include a diffusion barrier layer interposed between the dielectric layer and the bottom conductive layer. The diffusion barrier layer acts to inhibit atomic diffusion to at least a portion of the bottom conductive layer, particularly atomic diffusion of oxygen during formation or annealing of the dielectric layer. The container structures are especially adapted for use as container capacitors. The container capacitors are further adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.