Amorphous and gradated barrier layer for integrated circuit interconnects
US6465867B1 · kind B1 · utility
14Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2001 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Feb 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer, which has been implanted with a compounding material, lines the channel opening. A conductor core fills the opening over the barrier layer. The barrier layer having a dielectric layer proximate portion of a barrier compound varying into a conductor core proximate portion of a pure barrier material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.