Bonding pad structures for semiconductor devices and fabrication methods thereof
US6465895B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2001 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Apr 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a semiconductor structure, and a fabrication technique for forming such a structure, configured to confine and prevent expansion of cracking of the insulating layer below a bonding pad, that are generated as a result of the bonding process. In a first embodiment, the present invention includes a vertical frame, formed, for example of conductive material, surrounding the outer perimeter of the bonding pad, and extending through an underlying insulating layer. A horizontal frame lies below the vertical frame. Together, the vertical frame and horizontal frame confine cracks emanating below the bonding pad to within the frame region. In a second embodiment, horizontal and vertical portions of the frame are formed by a conductive layer provided in an opening formed in the insulating layer. Since the isolation frame prevents cracks from expanding into surrounding regions of the integrated circuit, overall process yield and reliability are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.