Method and apparatus for forwarding data in a hierarchial cache memory architecture
US6467030B1 · kind B1 · utility
7Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1999 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Nov 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for forwarding data in a hierarchial cache memory architecture is disclosed. A cache memory hierarchy includes multiple levels of cache memories, each level having a different size and speed. A command is initially issued from a processor to the cache memory hierarchy. If the command is a Demand Load command, data corresponding to the Demand Load command is immediately forwarded from a cache having the data to the processor. Otherwise, if the command is a Prefetch Load command, data corresponding to the Prefetch Load command is held in a cache reload buffer within a cache memory preceding the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.