Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner

US6468853B1 · kind B1 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Palanivel Balasubramanian · Singapore, SG
• Yelehanka Ramachandramurthy Pradeep · Singapore, SG
• Chivkula Subrahmanyam · Singapore, SG
• Narayanan Balasubramanian · Singapore, SG

Key dates

• Filing date: Aug 18, 2000
• Grant date: Oct 22, 2002
• Expiry date: Aug 18, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76235
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A structure and a process for manufacturing semiconductor devices with improved oxide coverage on the corners of a shallow trench isolation structure is described. The STI trench is etched using a pad oxide and silicon nitride layers as patterning elements. After trench etch, a thin conformal layer of either amorphous, epitaxial or polysilicon is deposited over the silicon nitride and within the trench and annealed. Where the silicon has been deposited on the silicon bottom and sides of the open trench, the annealing effectively forms a single crystal or epitaxial silicon. Next a silicon oxide liner is grown over the conformal silicon layer. The trench is then filled with silicon oxide, the structure is planarized by either chemical mechanical polishing or etching, and the nitride and pad oxide is removed This leaves a polysilicon film on the vertical edges of the filler oxide which extends slightly above the surface of the silicon substrate. A thermal oxidation step is performed converting the poly film into silicon oxide which slightly extends the STI field oxide into the active device region eliminating any reduced oxide coverage or oxide recesses in the corner regions.