Metal interconnection structure with dummy vias
US6468894B1 · kind B1 · utility
52Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Mar 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal interconnect structure and method of making the same provides a low k dielectric layer on a substrate that contains the first metal line. A plurality of vias are formed in the low k dielectric layer, along with a second metal line. A first set of the plurality of vias are connected between the first and second metal lines, and a second set of the plurality of vias are not connected between the first and second metal lines. The second set of vias form dummy vias that increase the mechanical strength of the via layer and increase the resistance to delamination and scratching during chemical mechanical polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.