System and method for eliminating pulse width variations in digital delay lines
US6469559B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Nov 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00039
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for eliminating pulse width variations in digital delay lines partitions a delay line into two substantially identical blocks of delay inverters, inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated and the only requirement is that the parasitic loading of the inverter between the blocks and the inverter on the output of the second block be the same. Consequently, the layout of the delay inverters in a single block may be made in the most efficient manner possible and the same identical layout can be used for the first and second blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.