Gate area relief strip for a molded I/C package
US6473311B1 · kind B1 · utility
7Cited by
2References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Jun 2, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49146
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and device for providing a relief area on the surface of a molded I/C package. Specifically, a method of reducing delamination at the gate area of a molded I/C package by disposing an area of patterned metal traces on the substrate surface to form a relief area. The relief area will permit the I/C package to be broken away form the molding apparatus while reducing the possibility of delamination or Au/Cu burs at the gate area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.