MRAM configuration
US6473335B2 · kind B2 · utility
11Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2001 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Jul 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.