Method of accurate simulation of logic circuits
US6473725B1 · kind B1 · utility
7Cited by
11References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1998 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Feb 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a logic simulation method, in which a signal is switched between two logic states to simulate a transition of a real signal. The method comprises the step of inserting between the two logic states of the signal an intermediate state for a time interval indicative of the slope of the transition of the real signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.