Implementing locks in a distributed processing system
US6473849B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1999 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Sep 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. The microcode within the lock requesting node transmits a write command to write corresponding node identification data into a lock register in the arbitrating node. The lock requesting node iteratively reads the lock register until it finds its node identification data stored therein with a valid bit set. The lock requesting node then informs all remaining processing nodes to release shared system resources. This is accomplished through a release request bit and a release response bit in each processing node. After completion of lock operations, the lock requesting node sends a message to the arbitrating node to reset the valid bit in the lock register, and a broadcast message to each remaining node to reset the release request bit. In an alternate embodiment, each processing node includes a lock resource register instead of a release response bit. Each remaining processing node writes its node identification data into the lock resource register within the lock reques…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.