Method for measuring source and drain junction depth in silicon on insulator technology
US6475816B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2001 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Apr 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/27
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is provided for accurately determining the junction depth of silicon-on-insulator (SOI) devices. Embodiments include determining the junction depth in an SOI device under inspection by measuring the threshold voltage of its “bottom transistor” formed by its source and drain regions together with its substrate acting as a gate. The threshold voltage of the bottom transistor of an SOI device varies with its junction depth in a predictable way. Thus, the junction depth of the inspected device is determined by comparing its bottom transistor threshold voltage with the bottom transistor threshold voltage of corresponding reference SOI devices of known junction depth to find a match. For example, simulated SOI devices with the same characteristics as the inspected device, whose junction depth and bottom transistor threshold voltages have been previously calculated, are used as a “reference library”. If the bottom transistor threshold voltage of the inspected device has about the same value as that of a particular one of the reference devices, then the inspected device has the junction depth of that particular reference device. Thus, junction depth of the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.